Achieving Fault Detection and Performance on CMPs

Technology scaling in integrated circuits has consistently provided dramatic performance improvements in modern microprocessors. However, increasing device counts and decreasing on-chip voltage levels have made transient errors a first-order design constraint that can no longer be ignored. Several proposals have provided fault detection and tolerance through redundantly executing a program on an additional hardware thread or core. While such techniques can provide high fault coverage, they at best provide equivalent performance to the original execution and at worst incur a slowdown due to error checking, contention for shared resources, and synchronization overheads. This work achieves a similar goal of detecting transient errors by redundantly executing a program on additional processor cores; however, by sacrificing a small degree of fault coverage, it speeds up (rather than slows down) program execution compared to the unprotected baseline case. This scheme exploits the fact that a small number of instructions are detrimental to overall performance, and selectively skipping them enables some cores to advance far ahead of others and obtain prefetching and large instruction window benefits. We highlight the incremental hardware required and show that reducing fault coverage from 100% to an average of 96%/81% can result in a speedup of 15%/150% for a collection of integer/floating point benchmarks.